Memory fault models, MBIST (Memory BIST) methods, and functional procedures.
The book describes on-chip decompression algorithms in Verilog, providing a realistic look at how these impact overall chip area and performance. Key Technical Coverage Digital System Test and Testable Design: Using ...
Gate-level faults, fault collapsing, and structural modeling in Verilog. Memory fault models, MBIST (Memory BIST) methods, and
It utilizes Verilog models and testbenches to implement fault simulation and test generation algorithms. Memory fault models
Random and deterministic test generation methods, plus sequential circuit test generation.